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V. PRACTICE EXERCISES/ACTIVITIES A NOR gate is also referred to as a NEGATED OR gate. It is the opposite or inverse of a simple OR gate. With the OR gate the output was forced to logic LOW (0) when both inputs were forced to logic LOW (0) and the output was logic HIGH (1) in all other situations, but with a NOR gate the output is forced to logic HIGH (1) when both inputs are forced to logic LOW (0) and the output is forced to logic LOW (0) in all other situations. For the NOR logic, the transistors are in parallel with the output above them so that if either or both of the inputs are high, the output is driven low. Using a Virtual Breadboard place all the components in the virtual breadboard in the Figure 1. 5 V INPUT OUTPUT 2002 A B A NOR B 10 kg 0 0 1 0 1 0 5 V 0 1 0 1 1 0 10 SV 21 Fiqure 1. NOR Gate Schematic Diagram