of 16 Which one(s) is/are correct? U O Select one or more: In ARM Cortex M3, the three phases of instructions executions can be completed in 3 clock cycles for all instructions In a 5 stage pipelining, the instruction latency will be 5 clock cycles In pipelining, all parts of the hardware are occupied by different instructions In pipelining, it is possible that two instructions are fetched in one clock cycle In a 3 stage pipeline, the throughput is 3 instructions per cycle. . Unsure 2 of 16 Which one(s) are correct about the ARM Cortex M3 operating mode? (You may choose multiple answers) Select one or more: Handler mode has two states: privileged and unprivileged An interrupt is an example that results in entering to handler mode 0 After reset, it enters thread mode In thread mode, ARM is in its normal program running state The processor enters thread mode as a result of an exception Insure 6 of 16 Which one(s) is/are correct about ARM Cortex M3 ? (you may choose multiple answers) Select one or more: D-code bus is 32 bits D-code bus is used for transferring instruction to the ARM Core processor I-code bus in Cortex M3 is 16 bits D I-code bus is used to transfer the data to the ARM Core processor Unsure 7 016 of 16 Which one(s) is/are correct about CISC and RISC architecture? (you may choose multiple answers) Select one or more: RISC architecture requires a bigger chip (hardware) CISC stands for Complex Instructions Set Computer O Variables-size instructions is one of the RISC features Load-store architecture is used in RISC architecture O CISC requires more complex tools In CISC architecture, a single instruction performs many operations sure