olowing register transters are to be executed in the bus system shown The 2below for hamissing information of the given table below for each time step: lete the missing information of the given table a- Compl m the Boolean control conditions of each register, memory and bus Setch the logic gates for register control conditions, Memory and the bus Write multiplexer (so, s1, s2) for each instruction Ske multiplexer and connect them to their appropriate location. b- T RTL S281So Load(LD) memory SO BuS BUS MUX si 8-1 T. | TRe_AR, LD IN CLR Memory Read Write 110 LD IN IR LOAD INR AC LOAD INR TR LOAD INR PC LOAD INR AR LOAD INR DR LOAD INR olowing register transters are to be executed in the bus system shown The 2below for hamissing information of the given table below for each time step: lete the missing information of the given table a- Compl m the Boolean control conditions of each register, memory and bus Setch the logic gates for register control conditions, Memory and the bus Write multiplexer (so, s1, s2) for each instruction Ske multiplexer and connect them to their appropriate location. b- T RTL S281So Load(LD) memory SO BuS BUS MUX si 8-1 T. | TRe_AR, LD IN CLR Memory Read Write 110 LD IN IR LOAD INR AC LOAD INR TR LOAD INR PC LOAD INR AR LOAD INR DR LOAD INR