ONLY CODE DATA PATH AND CONTROLLER PLEASE

PLEASE SHOW THE CODE Verilog

Design and construct a synthesizable Finite State Machine and Datapath which computes the greatest common denominator (GCD) of two numbers ( two 4-bit) numbers and output the binary value of the greatest common divisor of those two numbers.

Your design will consist of two components - the controller and the datapath. The controller is to be a pure FSM. The datapath operates based on signals generated by the controller FSM - it should have no independent controlling logic. ((datapath must be constructed structurally))

Use the GCD algorithm to help you with the code

The algorithim used to compute the GCD is as follows:

Step 1:Compare 2 numbers ( x = y ?). If so the the GCD is found.

Step:2: If x > y, then x = x - y. The two numbers are then compared once again.

Step 3:If y > x, then y = y - x. The two numbers are then compared once again.

Eample: x = 10 y = 2 Is x = y? No, x > y therefore x = x - y in our case, x = 10 - 2 = 8. Is x = y? No, x > y therefore x = x - y In our case, x = 8 - 2 = 6. Is x = y? No, x > y there fore x = x - y In our case, x = 6 - 2 = 4. Is x = y? No, x > y therefore x = x - y In our case, x = 4 - 2 = 2. Is x = y? Yes, therefore the GCD of 10 and 2 is 2.

The design of the GCD computer can be divided into 2 parts -

Controller and

Datapath.

The controller is an FSM which issues commands to the datapath based on the current state and the external inputs.

The controller basically steps through the GCD algorithim

The datapath contains functional units like multiplexors, registers, subtractors and a comparator.

If x = y, we have finished computing the GCD, and we go to the final state and assert the data output line.

The Datapath does the actual GCD computation. It has the following components:

Mux: takes 2 4-bit inputs and one select line. Based on the select line, it outputs either the 1st 4-bit number or the 2nd 4-bit number.

Register: Takes a 4-bit input, a load signal, reset, and a clock signal. If the load signal is high and the clock is pulsed, it outputs the 4-bit number.

Comparator: Takes 2 4-bit numbers, and assets one of 3 signals depending on whether the 1st number is less than, greater than or equal to the 2nd number.

Subtractor: Takes 2 4-bit numbers, subtracts the smaller number from the larger.

Output Register: Holds the GCD value. When x = y the GCD has been found and can be outputted. Because it is a register entity it should also take a clock and reset signal

The data path contains elements that need a control signal.

The selection signals of the multiplexers and the enable signals of the registers must have the right value at the right moment.

All of these signals are connected to the controller. This can best be described as a state machine.

Go to the final state and assert the data output line

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