Part 1. For a direct-mapped cache design with a 32-bit byte address, the 32 bits are divided into Tag/Index/Offset as follows: Index Offset 31-8 7-3 2-0 What is the cache block size (in bytes)? How many entries does the cache have? For each address in the given byte address sequence, fill the table below to specify the Index, Tag, whether the reference is a hit or a miss, and whether a replacement wl be triggered. Assume the cache is initially empty. Use hex- a. b. ecimal numbers for Index and Ta Hit/Miss Address 0x20038 0x20015 0x20038 0x20016 0x1A054 0x1B338 0x1B33F 0x20038 0x20113 Index Tag Replacement? Assume we have a fully associative cache with four-word blocks and a total size of 4 blocks. Use LRU replacement. a. Explain how a 32-bit byte address should be divided into Tag and Offset fields b. For the same byte-address sequence, fill in the table below. Assume the cache is Part 2. initially empty. Use hex-decimal numbers for Index and Tag. Column "LRU list" eil roi cei Address 0x20038 0x20015 0x20038 0x20016 0x1A054 0x1B338 Ox1B331F 0x20038 0x20113 Tag Hit/Miss Replacement? LRU List