Part V Figure $7$: A circuit that can select and display one of three characters.

After completing simulations of your code, make a Quartus project for this part of the exercise.

Include the required pin assignments for the DE$1-$SoC board for all switches, LEDs, and $7-$segment displays.

Compile the project.

Download the compiled circuit into the FPGA chip. Test the functionality of the circuit by setting the proper

character codes on the switches $S{W}_{5-0}$ and then toggling $S{W}_{9-8}$ to observe the rotation of the characters.

module fig$7($SW$,$ LEDR, HEX$0)$;

input $[9$:$0]$ SW; $//$ toggle switches

output $[9$:$0]$ LEDR; $//$ red LEDs

output $[6$:$0]$ HEx$0$; $//7-$seg displays

assign LEDR $=$ SW;

$//$ declare any wires needed

$...$ code not shown

$//$ instantiate module mux$\_2$bit$\_3$tol $($S$,$ U$,$ V$,$ W$,$ M$)$;

mux$\_2$bit$\_3$tol M$0(...)$;

$//$ instantiate module char$\_7$seg $($C$,$ Display$)$;

char$\_7$seg H$0(...)$;

endmodule

$//$ implements a $2-$bit wide $3-$to$-1$ multiplexer

module mux$\_2$bit$\_3$to$1($S$,$ U$,$ V$,$ W$,$ M$)$;

input $[1$:$0]$ S$,$ U$,$ V$,$ W;

output $[1$:$0]$ M;

$...$ code not shown

endmodule

$//$ implements a $7-$segment decoder for d$,$ E$,$ I and 'blank'

module char$\_7$seg $($C$,$ Display$)$;

input $[1$:$0]$ C; $//$ input code

output $[6$:$0]$ Display; $//$ output $7-$seg code

$...$ code not shown

endmodule

Figure $8$: Verilog code for the circuit in Figure $7.$ Table $2.$ Rotating the word dE$1$ on three displays.

Consider the circuit shown in Figure $7.$ It uses a two$-$bit wide $3-$to$-1$ multiplexer to enable the selection of three

characters that are displayed on a $7-$segment display. Using the $7-$segment decoder from Part IV this circuit can

display the characters $d,E,1,$ and 'blank'. The character codes are set according to Table $1$ by using the switches

$S{W}_{5-0},$ and a specific character is selected for display by setting the switches $S{W}_{9-8}.$

An outline of the Verilog code that represents this circuit is provided in Figure $8.$ We have used the circuits from

Parts III and IV as subcircuits in this code. You are to extend the code in Figure $8$ so that it uses three $7-$segment

displays rather than just one. You will need to use three instances of each of the subcircuits. The purpose of your

circuit is to display any word on the three displays that is composed of the characters in Table $1,$ and be able to

rotate this word in a circular fashion across the displays when the switches $S{W}_{9-8}$ are toggled. As an example, if

the displayed word is dE $1,$ then your circuit should produce the output patterns illustrated in Table $2.$

Perform the following steps.

Write Verilog code for your circuit that can display three$-$letter words. Your code should have the same

structure indicated in Figure $8,$ but supporting three displays HEX$2,$ HEX$1,$ and HEXO, rather than just

HEXO. In your Verilog code connect the switches $S{W}_{9-8}$ to the select inputs of each of the three instances

of the two$-$bit wide $3-$to$-1$ multiplexers that is needed for each display. Also, connect $S{W}_{5-0}$ to the data

inputs of these multiplexers in such a way as required to produce the patterns of characters shown in Table $2.$

Display the values of the $SW$ switches on the red lights LEDR, in addition to displaying your multiplexer

outputs on HEX$2,$ HEXI, and HEXO.

A top.v file is provided as part of the design files for this exercise, for use with the DESim tool. To use the

top. $v$ file directly, declare your Verilog module as:

module part$5($SW$,$ LEDR, HEX$2,$ HEX$1,$ HEX$0)$;

input $[9$:$0]$ SW;

output $[9$:$0]$ LEDR;

output $[6$:$0]$ HEX$2,$ HEX$1,$ HEX$0$;

endmodule