Pattern generator- verilog code

This must be coded in verilog

In this assignment we will program a sequential circuit in Verilog code as a pattern generator which generates, instead of binary counts, your Firstname (space) Lastname (space), character by character. Display the pattern sequence for at least two cycles (run the demo).

Suppose the output of the ripple sequencer is an arrray of q. Then, the truth table of encoding is:

 q0 q1 q2 q3 q4 ... ascii[6:0] char 1 0 0 0 0 ... 101 0111 = 'W' 0 1 0 0 0 ... 110 0101 = 'e' 0 0 1 0 0 ... 110 1001 = 'i' 0 0 0 1 0 ... 110 0100 = 'd' 0 0 0 0 1 ... 110 0101 = 'e' (etc.) 

Below is the code, the CoderMod module is the only one that needs to be completed. The size of the arrays in the other 2 modules might need to be adjusted. Please use "First [space] Lastname" for the name in the ascii code.

--------------------------------------------------------------------

module TestMod;

reg CLK;

wire [0:11] Q;

wire [6:0] ascii;

initial begin

#1;

forever begin

CLK=0;

#1;

CLK=1;

#1;

end

end

RippleMod my_ripple(CLK, Q);

CoderMod my_coder(Q, ascii);

initial #27 $finish;

initial begin

$display("Time CLK Q Name");

$monitor("%4d %b %b %c %x %b", $time, CLK, Q, ascii, ascii, ascii);

end

endmodule

module CoderMod(Q, ascii);

...

endmodule

module RippleMod(CLK, Q);

input CLK;

output [0:15]Q;

reg [0:15]Q;

always @(posedge CLK) begin

Q[0]

Q[1]

Q[2]

Q[3]

Q[4]

Q[5]

Q[6]

Q[7]

Q[8]

Q[9]

Q[10]

Q[11]

Q[12]

Q[13]

Q[14]

Q[15]

end

initial begin

Q[0] = 1;

Q[1] = 0;

Q[2] = 0;

Q[3] = 0;

Q[4] = 0;

Q[5] = 0;

Q[6] = 0;

Q[7] = 0;

Q[8] = 0;

Q[9] = 0;

Q[10] = 0;

Q[11] = 0;

Q[12] = 0;

Q[13] = 0;

Q[14] = 0;

Q[15] = 0;

end

endmodule

----------------------------------------------------

Thanks!

Link to assignment if needed: http://athena.ecs.csus.edu/~changw/137/prg/5PatternGenerator/

Pattern Generator Ripple Sequence Generator 5 7 (ASCII) Pattern Encoder CLK Ripple Sequence Generator CLK