PCSrc ID/EX EX/MEM Control F/ID Ad MEM/WE ranc hi left 2 4 Read Addr 1 Instruction Memory Data Register Read : Read Addr Data 1 Memory File rite Addir Address Read Data Address ALU Read Data 2 Write Data rite Data AL Sign 32 Extend cntrl Forward Unit 4. On the datapath shown on slide 3 of lecture 16, add circuitry to allow for data forwarding from the data memory. Please redraw the figure, including the neces- sary new hardware and wires needed for the forwarding. Only include hardware for memory data forwarding. 5. Consider the instruction lw $t1, 8($so). Use the datapath shown on slide 3 of lecture 16 for vour answer: (a) What is this instruction in binary format? (b) What is the output of the sign extend unit for this instruction as it is (c) What is the input value of "Read Addr 1" in the ID stage? How big is (d) Assuming the instruction is located at address Ox400C, what is the (e) If the longest stage of the pipeline requires 300ps, what is the latency exits the ID stage the input:? value of the PC after the IF stage? of the instruction? What is the throughput of the pipeline? PCSrc ID/EX EX/MEM Control F/ID Ad MEM/WE ranc hi left 2 4 Read Addr 1 Instruction Memory Data Register Read : Read Addr Data 1 Memory File rite Addir Address Read Data Address ALU Read Data 2 Write Data rite Data AL Sign 32 Extend cntrl Forward Unit 4. On the datapath shown on slide 3 of lecture 16, add circuitry to allow for data forwarding from the data memory. Please redraw the figure, including the neces- sary new hardware and wires needed for the forwarding. Only include hardware for memory data forwarding. 5. Consider the instruction lw $t1, 8($so). Use the datapath shown on slide 3 of lecture 16 for vour answer: (a) What is this instruction in binary format? (b) What is the output of the sign extend unit for this instruction as it is (c) What is the input value of "Read Addr 1" in the ID stage? How big is (d) Assuming the instruction is located at address Ox400C, what is the (e) If the longest stage of the pipeline requires 300ps, what is the latency exits the ID stage the input:? value of the PC after the IF stage? of the instruction? What is the throughput of the pipeline