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Consider the following assembly code: Instruction Description LOAD R1, M1 Read data from memory address M1 and store in R1. LOAD R2, M2 Read data from memory address M2 and store in R2. OR R5, R1, R2 JUMP Target 1 Target2: XORR2, R1, R1 Logical Ex-OR between contents of R1 with R1 and store result in R2 Target 3: ADD R7, R1, R5 Add contents of R1 and R5 and store to R7 OR R2, R4, R6 Logical OR between contents of R4 with R6 and store result in R2 OR R5, R3, R7 ADDR5, R7, R3 AND R1, R2, R3 Target 1: SUB R3, R1, R2 Subtract content of R2 from R1 and save result in R3; here R1 = R2 BNEZ R3, Target2 Jump to Target2 if R3 is non-Zero BEZ R3, Target3 Jump to Target3 if R3 is Zero OR R2, R4, R6 Logical OR between contents of R4 with R6 and store result in R2 STORE M4, R2 Save contents of R2 to memory address M4 END Use five-stage pipeline containing Fetch, Decode, Memory read, Execute. Write-back units, show the execution of program (at least 20 time steps). Data dependencies and control hazards, if detected must be resolved by delaying the pipeline as required. Use the following format: Instructions Time-step 1 2 3 4 5 LOAD R1. Mi LOAD R2, M2 OR R5, R1, R2 JUMP Target 1 Target2: XOR R2, R1, R1 Target3: ADD R7, R1, R5 OR R2, R4, R6 OR R5, R3, R7 ADDR5.R7, R3 AND R1, R2, R3 Target 1: SUB R3, R1, R2 BNEZ R3, Target2 BEZ R3, Target3 OR R2, R4, R6 STORE M4, R2 END