Please do it ASAP Exam Question!

5: [15pts]. Design a synchronous circuit to detect the 1001 pattern in the input sequences W using FSM method. The result is Z. An example of the desired behavior is: A: Derive the state diagram for the FSM. [5pts] B: Write the complete Verilog code for the FSM. [10pts] Note: using the synchronous design methodology and ALL storaye elements work in the rising edge of the clk