please dont add thiis solution its my third time asking this question, dont copy and paste, this solution is not complete

Question 4 (20 pts.): The data path is given for a 4-bit multiplier. It consists of a 4-bit adder, a 4-bit register, and a 9-bit shift register. The latter shifts right when its Sh input is asserted (assume that O's are entered at the left for this operation). A new value is loaded into the high-order 5 bits of the shift register when Ld is asserted. The same 5 bits are zeroed when Cl is asserted These signals are synchronous. Design the control for a sequential 4-bit multiplier. 4-bit Multiplier M Sh La ci Shift right 4-bit Multiplicand s Control Unit Sh Ld cl Carry Out + a. (10 pts.) Sketch a complete state diagram for the operation of the Control Unit. b. (10 pts.) Sketch a logic implementation of the Control Unit using D-type flip-flops and logic gates of your choice using one-hot state assignment. You do not have to show the transition/state tables. The duign look at the bit of mulbilier and if it is o Answer for 2: fer ginen data & information Here, the multiplication in the continews adelition il do nothing on the partial predwet is o. if it is 1 it add the multiplication and the partial Product . The product seguito hold the multiplication semella Ok the proceset succinter is cleared intially, and the multiplein Shefte one kit to the right sto obow the wont let The partial product is located to the higher - order 5 bits and this is added to the multiplie and when . The result in Shifted onu liefde the load - The Mystero takus cycles to compute the result. The first Cycle is to the clear the product Meguiter In the semaining 4 eyeles the circuit obterme the the lower - leit of the multiplier and perform additions based on that values If the value in '1', it loadi and Shifte the value is 'o' it simply Shifts. the bit is 1. values it The control for a sequential 4 bit multiplier Reset Cidler slee So Question 4 (20 pts.): The data path is given for a 4-bit multiplier. It consists of a 4-bit adder, a 4-bit register, and a 9-bit shift register. The latter shifts right when its Sh input is asserted (assume that O's are entered at the left for this operation). A new value is loaded into the high-order 5 bits of the shift register when Ld is asserted. The same 5 bits are zeroed when Cl is asserted These signals are synchronous. Design the control for a sequential 4-bit multiplier. 4-bit Multiplier M Sh La ci Shift right 4-bit Multiplicand s Control Unit Sh Ld cl Carry Out + a. (10 pts.) Sketch a complete state diagram for the operation of the Control Unit. b. (10 pts.) Sketch a logic implementation of the Control Unit using D-type flip-flops and logic gates of your choice using one-hot state assignment. You do not have to show the transition/state tables. The duign look at the bit of mulbilier and if it is o Answer for 2: fer ginen data & information Here, the multiplication in the continews adelition il do nothing on the partial predwet is o. if it is 1 it add the multiplication and the partial Product . The product seguito hold the multiplication semella Ok the proceset succinter is cleared intially, and the multiplein Shefte one kit to the right sto obow the wont let The partial product is located to the higher - order 5 bits and this is added to the multiplie and when . The result in Shifted onu liefde the load - The Mystero takus cycles to compute the result. The first Cycle is to the clear the product Meguiter In the semaining 4 eyeles the circuit obterme the the lower - leit of the multiplier and perform additions based on that values If the value in '1', it loadi and Shifte the value is 'o' it simply Shifts. the bit is 1. values it The control for a sequential 4 bit multiplier Reset Cidler slee So