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The following register transfers are to be executed in the system of Fig. 5-4. For each transfer, specify (1) the binary value that must be applied to bus select inputs S_2, S_1, and S_0; (2) the register whose LD control input must be active (if any); (3) a memory read or write operation (if needed); and (4) the operation in the adder and logic circuit (if any). a. AR leftarrow PC