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Please help with question 4.d) [6] logic design 1201 Consider the following sequential circuit with two negative-edge-triggered JK flip-flops. Q1 02 Q1 QI CK 02

Please help with question 4.d) [6] logic design image text in transcribed
1201 Consider the following sequential circuit with two negative-edge-triggered JK flip-flops. Q1 02 Q1 QI CK 02 12 Q2 CK K2 CLR K1 Clock 4.a) [21 Complete the timing diagram for the above circuit. CLR JI KI o1 K2 - 19 4d) (61 From the analysis of the circuit above, draw the state table and the state graph

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