Please I need help with the following questions 1 Describe how the Mov R23, $12CD instruction would work on the following architecture This instruction moves the value hex 12CD into register 2 and register 3 with register 2 being the most significant byte 2 Describe the hardware required to implement the Addc R1, $FC12,R2 instruction This instruction adds the value $FC12 to the contents of register to resulting in a memory address The value at that address is read and added to the contents of register 1 along with the current value of the carry flag The result is stored in register 1 This instruction may require several clock cycles depending on how you implement it as well as several pieces of hardware Implement it however you like Any hardware you add should start with U600 to preclude using a number already used 3 Briefly describe how the xor R0,R1 would work on using the architecture 4 Briefly describe what hardware inputs outputs would need to be added to implement the following instruction xor R3,$35 Exclusive or the value $35 with the contents of register 3 and store the result in register 3 DATAp 1 5 115 INSTR0 15 IP IP 0 15 IPine 2 MUX RiPDo IP 0 15 IP 116 IP SPo 15 INST0 15 ckInst Pointer 0 15 Mem Addr Selp I MUX 105 Selo 1 500 IP 106 Sumo 15 MEM 1 Inst Len Inst Len Sumo 15 DATA0 15 Offsct MEM 2Instruction Offset Register Decodeir 32 Bit INSTR 15 INST0 15 MEM 3 Control MEM 4 NOTE Every time an instruction is fetched, 4 memory reads are done in sequence to file the instruction register This is completed before any other actions are taken The output of the Instruction Decode register are held constant until this Instruction Fetch cycle is completed DATAp 1 5 115 INSTR0 15 IP IP 0 15 IPine 2 MUX RiPDo IP 0 15 IP 116 IP SPo 15 INST0 15 ckInst Pointer 0 15 Mem Addr Selp I MUX 105 Selo 1 500 IP 106 Sumo 15 MEM 1 Inst Len Inst Len Sumo 15 DATA0 15 Offsct MEM 2Instruction Offset Register Decodeir 32 Bit INSTR 15 INST0 15 MEM 3 Control MEM 4 NOTE Every time an instruction is fetched, 4 memory reads are done in sequence to file the instruction register This is completed before any other actions are taken The output of the Instruction Decode register are held constant until this Instruction Fetch cycle is completed

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Please I need help with the following questions! 1. Describe how the Mov R23, $12CD instruction would work on the following architecture. This instruction moves

Please I need help with the following questions!

1. Describe how the "Mov R23, $12CD" instruction would work on the following architecture. This instruction moves the value hex 12CD into register 2 and register 3 with register 2 being the most significant byte.

2. Describe the hardware required to implement the Addc R1,[$FC12,R2] instruction. This instruction adds the value $FC12 to the contents of register to resulting in a memory address. The value at that address is read and added to the contents of register 1 along with the current value of the carry flag. The result is stored in register 1. This instruction may require several clock cycles depending on how you implement it as well as several pieces of hardware. Implement it however you like. Any hardware you add should start with U600 to preclude using a number already used.

3. Briefly describe how the xor R0,R1 would work on using the architecture.

4. Briefly describe what hardware/inputs/outputs would need to be added to implement the following instruction: xor R3,$35. Exclusive-or the value $35 with the contents of register 3 and store the result in register 3.

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DATAp-1:5 115 INSTR0-15 IP IP 0-15 IPine 2 MUX RiPDo IP 0-15 IP 116 IP SPo-15 INST0-15 ckInst Pointer 0-15 Mem Addr Selp-I MUX 105 Selo-1 500 IP 106 Sumo-15 MEM 1 Inst Len Inst Len Sumo-15 DATA0-15 Offsct MEM 2Instruction Offset Register/ Decodeir 32-Bit INSTR-15 INST0-15 MEM 3 Control MEM 4 NOTE: Every time an instruction is fetched, 4 memory reads are done in sequence to file the instruction register. This is completed before any other actions are taken. The output of the Instruction / Decode register are held constant until this Instruction Fetch cycle is completed DATAp-1:5 115 INSTR0-15 IP IP 0-15 IPine 2 MUX RiPDo IP 0-15 IP 116 IP SPo-15 INST0-15 ckInst Pointer 0-15 Mem Addr Selp-I MUX 105 Selo-1 500 IP 106 Sumo-15 MEM 1 Inst Len Inst Len Sumo-15 DATA0-15 Offsct MEM 2Instruction Offset Register/ Decodeir 32-Bit INSTR-15 INST0-15 MEM 3 Control MEM 4 NOTE: Every time an instruction is fetched, 4 memory reads are done in sequence to file the instruction register. This is completed before any other actions are taken. The output of the Instruction / Decode register are held constant until this Instruction Fetch cycle is completed