Please provide full code.test and show working proof in quartus$/$ multi sim software.

provide final code along with final code test bench.

private code for individual modules along with test benches for individual modules. $!!$

Pre$-$Requisite

The theoretical$/$practical background required for this project is provided in the Lecture$/$Lab

sessions. To undertake this project, students should be able to:

Use Quartus II and ModelSim software in the design, synthesis and simulation of digital

systems

Model digital logic components using VHDL

Implement a design onto a target FPGA development board

Project description

The aim of this assignment is to apply VHDL design concepts to solve an engineering problem.

Students are required to design and develop a Real$-$time Clock using an Altera DE$-$O development

board. The requirements of the Digital Clock are as follows:

The time is displayed using the four seven$-$segment displays in the format

hh$.$mm @ The time

will range from $12$:$00$am to $11$:$59pm,$ repeating.

A single decimal point will be used in place of the colon, e$.$g$.1\mathrm{.}15$

Employ zero suppression for the leading digits, e$.$g$.$ for single digit times such as $1$:$15,$ do

not display as $01$:$15$

The PM period of the day should be indicated by an LED

A slide switch can be used to set the time. When setting the time, the following must apply:

When the slide switch is in the zero position, the clock operates normally.

When the slide switch is in the one position, the time can be set starting from the left

most digit

The three push$-$button switches will be used to set the time

Push button $1-$ increment value

Push button $2-$ decrement value

Push button $3-$ move on to the next digit

Wraparound values must be taken into consideration

After the desired time has been set, the slide switch will be placed back in the zero

position and the clock will continue displaying time from the set point.