Please solve all the above mentioned questions

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8.1 Complete the timing diagram for the given circuit. Assume that both gates have a propagation delay of 5 ns. W DD- W V Y Y 0. 10 15 20 25 30 35 40 t(ns) 8.2 Consider the following logic function. %3D (a) Find two different minimum circuits which implement F using AND and OR gates. Identify two hazards in each circuit. (b) Find an AND-OR circuit for F which has no hazards. (c) Find an OR-AND circuit for F which has no hazards. 8.3 For the following circuit: B E (a) Assume that the inverters have a delay of 1 ns and the other gates have a delay of 2 ns. Initially A = 0 and B = C = D = 1, and C changes to 0 at time = 2 ns. Draw a timing diagram and identify the transient that occurs. (b) Modify the circuit to eliminate the hazard.