Practice Problem 1: Suppose you are employed in a company and on a very first day you have been given a task to design an elevator using FPGA that covers three floors, Ground floor, First floor and Second floor. The elevator is initially assumed to be at the ground floor with its door open. If a destination is given from the ground floor, the destination indicator of that floor is turned on and the door closes. When the elevator reaches the destination, the door opens and the indicator turns off. If the elevator is called from another floor, the door closes and the call indicator of the floor calling is turned on. The elevator takes 3secs to move from one floor to the next Can you please write above design in Verilog HDL so that your boss can tell Software to synthesize circuit