Problem #1 We assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline (IF, ID, EX, MEM, WB), data forwarding unit (only from MEM and WB stages to EX stage), hazard detection unit, and branch instruction outcome and target address are known in MEM stage. Assume that the first half of the clock cycle write-back stage writes to register file and the second half of the clock cycle the decode stage performs a read of source registers. Show a pipeline execution diagram for the program where all data forwards are marked with arrows and stalls are marked with **. You can insert NOPs in addition to stalls (if needed for the correct operation of the code). I1: lw $4, 4($16) I2: add $5, $4, $2 I3: lw $6, 8($5) I4: beq $5, $6, Target I5: sub $3, $5, $6