Problem 10.

The following sequence of MIPS instructions is executed in the pipelined architecture. the registers are: S * 2 = 2 . S * 3 = 3 S * 4 = 4 . S * 5 = 5 , S * 6 = 6 . S * 7 = 7 SS = 8 and \$ 9 = 9 .

add $8, $2, $3

add

$9, $5, $6

add $7, $8, $9

add $10, $11, $12 add $13, $14, $15.

(a) During the fifth cycle of execution (see the figure in the below), determine the followings. 425 8 ID/EX.Rs (the first source register number for instruction in EX stage)="7

pL = 9

(b) What are the three input value candidates for the first operand to the ALU (ie, three input values to the first

ID/EX.Rt (the second source register number for instruction in EX stage) = EX/MEM.Rd (the destination register number for instruction in MEM stage) 2 * d = 4 3 MEM/WB.Rd (the destination register number for instruction in WB stage) = 8

MUX in the EX stage in the figure)? 8, 5, 11

(c) Among the three input value candidates in (b), which value is selected as the first operand to the ALU? 5

(d) What are the three input value candidates for the second operand to the ALU (ie, three input values to the

second MUX in the EX stage in the figure)? 4,5,!!

(e) Among the three input value candidates in (d), which value is selected as the second operand to the ALU? E

add $10,$11,$12

add $7.$8,$9

add $9,$5.$6 add $8,$2,$3

Assume the initial value of

EXUMEM

instruction