PROBLEM 2 (15 PTS) . Complete the timing diagram of the following circuit, which computes integer square root using a binary search approach. n = 12. Note that rm = 1 1/ rf > D, else 0, re 1 if = D, else 0. Shift registers: serial input is . The value of D is an unsigned decimal. FSM: j is an embedded counter, j changes on the clock edge. FSM 100..0 1000.0 2n 01o...0 00010..0 2 RIGHT data-a data atk comp 2n FSM dane 1 clock esetn 22n-4 tate S1 PROBLEM 2 (15 PTS) . Complete the timing diagram of the following circuit, which computes integer square root using a binary search approach. n = 12. Note that rm = 1 1/ rf > D, else 0, re 1 if = D, else 0. Shift registers: serial input is . The value of D is an unsigned decimal. FSM: j is an embedded counter, j changes on the clock edge. FSM 100..0 1000.0 2n 01o...0 00010..0 2 RIGHT data-a data atk comp 2n FSM dane 1 clock esetn 22n-4 tate S1