Problem #2 A 4-byte cache, with 2-byte blocks receives the following 4-bit address sequence generated by the microprocessor (represented in binary): 0001, 0010, 0100, 0000, 0011, 0101 Draw the hardware architecture and determine the hit ratio for the given access pattern if the cache is (i) a direct mapped cache and (ii) a fully associative cache (using LRU replacement). Assume that cache is initially empty for each cache organization. Show your work to get full credit.