An 8-byte, 2-way set-associative cache (using LRU replacement) with 2-byte blocks receives requests for the following addresses (represented in binary):

0110, 0000, 0010, 0001, 0011, 0100, 1001, 0000, 1010, 1111, 0111

Draw the hardware organization of the cache and compute the total size of the cache in bits. The cache uses a write-back policy. Assume that cache is initially empty. For each access, determine the address in the cache (after the access), whether each access hits or misses. Determine also the hit ratio.