Question 3: Here you are asked to show how one particular sequence of memory references would perform in terms of hit and miss) on a 2 way set-associative cache. The size of cache is 4 blocks and the cache block size is 4-byte. The memory is addressed by byte. Suppose the following sequence of memory references arrive at cache in order Reference #1> Address: 000000110 Reference #2> Address: 000000100 Reference #3> Address: 001 000010 Reference #42 Address: 000001000 Reference #5> Address: 011 001 000 Specify if the memory references are a cache miss or hit. Then use the tables below to show the state of the cache just after every memory reference completes. 2-Way Set-Associative: initial state Set (1-bit Valid Tag (6-bit) Data (4-byte 2-way Set-Associative after reference #1 Set (1-bit) Valid Tag (6-bit) Data (4-byte) 2-way Set-Associative: after reference #2 Set (1-bit) Valid (6-bit) Data (4-byte) 2-Way Set-Associative: after reference #3 Set (1-bit) Valid Tag (6-bit) Data (4-byte 2-Way Set-Associative, after reference #4 Set (1-bit) Valid Tag (6-bit) Data (4-byte) 2-Way Set-Associative after reference #5 Set (1-bit) Valid Tag (6-bit) Data (4-byte