Problem 2 TLB and Address Mapping Virtual memory uses a page table to track the mapping (i.e. translation) of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. Assume it has 4-Kbyte pages, a 4-entry fully-associative TLB with a true LRU replacement scheme. If a page must be brought in to the main memory due to a page fault, it is placed in the page with the page number equals to the largest page number incremented by 1, ie. if the current largest physical page number is 12 as shown in the table below, it will be placed in the page number 13The following list shows the stream of virtual addresses as seen on the system. 4669, 2227, 13916, 34587, 48870, 12608, 49225 The content of TLB and page table is shown in the following two tables. TLB Valid Bit sical Page Number Page Table sical Page Number or on Disk Disk Disk Disk Disk Do 2.b on Please. Proble Please show the final Also, lis the TLB ar ven the address stream shown above. ence if it is a hit in the TLB, a hit in the or a page fault Problem 2.b Repeat Problem 2a, but use 16-Kbyte pages instead of 4-Kbyte pages. What would be the advantages of having a larger page size? What are the disadvantages? Problem 2.c Show the final content of TLB if it is 2-way set associative, instead of fully associative. Also show the final content of TLB if it is direct mapped. Discuss the importance of having a TLB to high performance, i.e. how would virtual memory accesses be handled if there were no TLB? There are several parameters that can impact the overall size of the page table. List below are the key page table parameters. Virtual Address Size Page Size & Kb bits Problem 2.d Given the parameters shown above, calculate the total page table size (in bytes) for a system running 5 applications. Each has its own page table, i.e. there are 5 page tables exist at the same ime in the system. Assume cach application utilizes half of the virtual memory space. Problem 2.e Repeat Problem 2.d, but assume a 2-level page table with 256 entries in the first level page table. Also assume that each entry of the first-level page table has 6 bytes. Problem 2 TLB and Address Mapping Virtual memory uses a page table to track the mapping (i.e. translation) of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. Assume it has 4-Kbyte pages, a 4-entry fully-associative TLB with a true LRU replacement scheme. If a page must be brought in to the main memory due to a page fault, it is placed in the page with the page number equals to the largest page number incremented by 1, ie. if the current largest physical page number is 12 as shown in the table below, it will be placed in the page number 13The following list shows the stream of virtual addresses as seen on the system. 4669, 2227, 13916, 34587, 48870, 12608, 49225 The content of TLB and page table is shown in the following two tables. TLB Valid Bit sical Page Number Page Table sical Page Number or on Disk Disk Disk Disk Disk Do 2.b on Please. Proble Please show the final Also, lis the TLB ar ven the address stream shown above. ence if it is a hit in the TLB, a hit in the or a page fault Problem 2.b Repeat Problem 2a, but use 16-Kbyte pages instead of 4-Kbyte pages. What would be the advantages of having a larger page size? What are the disadvantages? Problem 2.c Show the final content of TLB if it is 2-way set associative, instead of fully associative. Also show the final content of TLB if it is direct mapped. Discuss the importance of having a TLB to high performance, i.e. how would virtual memory accesses be handled if there were no TLB? There are several parameters that can impact the overall size of the page table. List below are the key page table parameters. Virtual Address Size Page Size & Kb bits Problem 2.d Given the parameters shown above, calculate the total page table size (in bytes) for a system running 5 applications. Each has its own page table, i.e. there are 5 page tables exist at the same ime in the system. Assume cach application utilizes half of the virtual memory space. Problem 2.e Repeat Problem 2.d, but assume a 2-level page table with 256 entries in the first level page table. Also assume that each entry of the first-level page table has 6 bytes