Project description:

In this project, we need to upgrade our accumulator computer described and implemented in the example above to a

bit more complicated computer. The memory in this computer system is $16-$bit cell memory with size of $128$ cells

$($i$.$e$.$ cell width $=16$bits$).$ The memory is synchronous to the CPU, and the CPU can read$/$write one cell in a

single clock cycle. The memory can only be accessed through the memory address register $($MAR$)$ and the

memory buffer register $($MBR$).$

The CPU has a program counter $($PC$)$ register and an instruction register $($IR$).$ This CPU has eight $16-$bit

general$-$purpose registers R$0-$R$7.$

The $16-$bit instruction format is as follow:

Opcode$(3$bits$)$ Dst$.$ Register $(3$bits$)$ mode $(2$bits$)$ Src$.$ Register$/$ Memory Address $(8$bits$)$

Addressing Modes bits for the last field of the instruction $(8$bits$)$:

$00=>$ Direct memory address

$01=>$ Register

$10=>$ Register Indirect

$11=>$ Constant

The opcodes are:

$000$ LOAD Ri$,$ operand: loads register Ri with a memory cell of address operand$/$register content of address operand$/$

memory cell of address in register operand$/$or a constant integer operand.

$001$ STORE Ri$,[$M$]$: Stores the contents of Ri in memory cell of address M$.($only mode$=00$ is supported with store

instruction$)$

$010$ ADD Ri$,$ operand: Adds the contents of Ri to the operand, and store the result in Ri$.$

$011$ SUB Ri$,$ M: subtract the contents operand from Ri and store the result in Ri$.$

$0100$ MUL Ri$,$ M: Multiplies the contents of Ri by the operand, and store the result in Ri$.$

$0101$ DIV Ri$,$ M: Divides the contents of operand by Ri and store the result in Ri$.$

Assume data is singed $16-$bit integers in two$$s complement format.

Example:

To add memory cell of address $8$ with a constant $9,$ and store the result in memory cell of address $10,$ we can

use the following program:

Assembly Machine code$[$binary$]$ Machine code$[$Hex$]$

Load R$0,[8]00000000000010000$x$0008$

Load R$1,900000111000010010$x$0709$

Add R$0,$ R$101000001000000010$x$4101$

Store R$0,[10]00100000000010100$x$200$A

Requirements:

$1)$ a$-$ How many instructions this machine can support $[$i$.$e$.$ max$]?$

b$-$ What is the range of unsigned and signed constant numbers this machine supports?

c$-$ What is the length $($in bits$)$ of the following registers in this machine?

PC:

IR:

MAR:

MBR:

$2)$ Simulate the following program by converting each instruction to corresponding machine code. Then store the

machine code in memory starting from location $10$:

Memory Address Contents

$10$ Load R$0,[20]($instruction$)$

$11$ Load R$1,21($instruction$)$

$12$ Add R$0,[$R$1]($instruction$)$

$13$ load R$1,[22]($instruction$)$

$14$ Sub R$1,+8($instruction$)$

$15$ Add R$0,$R$1($instruction$)$

$16$ Store R$0,[23]($instruction$)$

$206($data$)$

$21-4($data$)$

$2213($data$)$

$230($data$)$

$240($data$)$

Verify that it works correctly and the also verify that the result stored at address $24$ is correct. Attach simulation

waveform and the Verilog source file.

$3)$ Assume A$,$B$,$C$,$D$,$E and Y are memory cells with addresses $25,26,27,28,29,$ and $30,$ respectively.

Given $,=$

$+5$

$+2$

$,$

a$)$ Write assembly code for implementing the above arithmetic expression?

b$)$ Convert the above assembly instructions into machine code $[$Hex$]$ and store them in the memory starting at

address $10.$

address content

$10$

$11$

$12$

$13$

$14$

$15$

$16$

$17$

$18$

$19$

$20$

c$)$ Set PC$=10$ and simulate the above program. Verify that it works correctly and the result stored at memory

variable Y is correct. Attach simulation waveform and the Verilog source file. Assume A$,$ B$,$ C$,$ D and E have

the values $18,3,4,8,$ and $-3,$ respectively.

What to submit:

Each group needs to submit the followings within the specified deadline by any partner:

$-$ All Verilog code for each required simulation

$-$ A short report $2-3$ pages includes the project design and implementation including your answers to the

above questions. It should also include code and simulation waveforms for each required simulation task.

$-$ The report should include a section illustrating the role and tasks achieved by each team member.