Q. Consider the following sequence of memory references in a 16 bit processor.

Please explain your answer.

Consider the following sequence of memory references in a 16-bit processor Address (hex) Type A000 B000 A380 A004 A108 5800 A10C A39C A3AC A1AC A006 Assume a data cache organization where the capacity is 4KB, line size is 64 bytes, the cache is direct- mapped, and has write-back, write-allocate policy. For each reference, is it a hit or a miss? For each reference, does it prompt a write-back of a dirty block to the next level of the cache? Show for each step, the contents of the cache including the tag. For simplicity, assume that the content of a memory address is the same as its memory address; i.e., mem[X) = X