Write a description of a 4-bit up counter named by1or2. The counter increments on a positive clock edge only if its active low enable (cnten_bar) is asserted. If its by2 input is
asserted, the counter increments by 2; otherwise, it increments by 1. If the counter overflows it continues to count from 00000. The counter has an active-low asynchronous reset (rst_bar) and an active-low synchronous clear (clr_bar).