Q1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as decimal word addresses.

a. 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253

b. 21, 166, 201, 143, 61, 166, 62, 133, 111, 143, 144, 61

For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. You can fill out a table like the given references.

a) 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253

Number	Binary Address	Tag	Index	Hit/Miss
3
180

b) 21, 166, 201, 143, 61, 166, 62, 133, 111, 143, 144, 61

Number	Binary Address	Tag	Index	Hit/Miss
21
166

Q2. Suppose we have a byte addressable memory of size 4GB (2^32 bytes). We are given a cache

of size of 256K MB L2 cache (2^17 bytes, not including tag bits) and a cache block size of 64

(2^6 ) bytes. The L2 cache is 8-way (2^3 ) associative. Compute for the L2 cache the length in number of bits for the tag, index and offset fields of a 32-bit memory address (show your calculations)

Q3. Considering the answer to part (a), circle the bits representing the index in the following 32-bit memory address (in binary):

10011101110001101110100111000100

Q4. A computer system has a 1 GB main memory. It also has a 4K-Byte cache organized as a 4way set-associative, with 4 blocks per set and 64 bytes per block. Calculate the number of bits in the Tag, Set Index, and Byte Offset fields of the memory address format.

Q5. Consider a processor with a 2 ns clock cycle, a miss penalty of 20 clock cycles, a miss rate of 0.05 misses per instruction, and a cache access time (hit time) of 1 clock cycle. Assume that the read and write miss penalties are the same.

a) Find the average memory access time (AMAT).

b) Suppose we can improve the miss rate to 0.03 misses per instruction by doubling the cache size. However, this causes the cache access time to increase to 1.2 cycles. Using the AMAT as a metric, determine if this is a good trade-off.

c) If the cache access time determines the processors clock cycle time, which is often the case, AMAT may not correctly indicate whether one cache organization is better than another. If the processors clock cycle time must be changed to match that of a cache, is this a good tradeoff?

Assume that the processors in part (a) and (b) are identical, except for the clock rate and the cache miss rate. Assume 1.5 references per instruction (for both I-cache and D-cache) and a CPI without cache misses of 2. The miss penalty is 20 cycles for both processors.