Q1. For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. (4 points) Index 9-5 Offset 4-0 Tag 31-10 a) How many words of data in each cache line? b) How many lines does the cache have? c) What is the cache data size (in bits)? d) What is the ratio between total bits required for such a cache implementation over the data storage bits