Q1: Given the following Combinational circuit, Use Verilog HDL on Quartus tool to LO 11 12 4 to 1 MUX I I S, So 2 to 1 MUX Output S2 14 IS 16 I. 4 to 1 MUX S, So 1. Write a Verilog HDL code to describe the module mux 4x1 // this module name must be your last name 2. Write a Verilog HDL code to describe the module mux2x1// this module name must be your first name 3. Write a Verilog HDL code to describe the whole system structurally from its subsystems // this module name must be your university number