{Q-2} Suppose we are working with an architecture that has 4 registers (SRO,SR1,$R2 and $R3) and the memory is word-addressed. The instruction set for this architecture consists of the following operations: add op 1, op2 op 1 = op 1 + op2 sub op, op 2 op 1 = op1 - op2 move op1, op2 op 1 = op2 and the addressing modes are as follows: immediate # Register $Ri Direct label or number Indirect @ Shift n($RI) Auto-increment shift n($Ri)+ (after calculating the address of the operand it increments $Ri by 1). In an instant of time the registers and memory have the following state: CPU registers : $RO O $R11 $R20 $R32 MEMORY: 02 14 23 37 48 50 61 79 84 94 103 AN ONONOO O OOOO Given the following code and symbol table, show how the registers and memory are modified move $R1, #4 move SRO, 2@ move SR2, B add $R2, 2($R1) move C, @$RO move SRO, @4 (SR1 A6 B3 como C5 Symbol table@