Q23. (a) The output of the front end stage shows 6 uops streams coming into the execution engine. 6 uops emerge from the Rename/Allocate/Retirement/ReOrder Buffer as well. From this the sustained number of the simultaneously issued instructions should be 6 (width of the front end). (3 marks) (b) There are 9 integer execution units and 3 floating point execution units shown in the execution engine. Therefore, ideally, 12 instructions can start execution simultaneously if the conditions are right (no dependencies), and they were buffered in the a.m buffer beforehand. (3 marks) (c) D cache memory caches data, and I cache memory caches instructions which allows resolving the von Neuman bottleneck close to the CPU core (implementing the Harvard memory architecture). The higher the number of the cache level, the further away is the cache from the CPU core; bigger size; slower access. Both caches are set-associative; however the D-cache has 8 way associativity that provides better hit rate than the 4 way associativity of the l-cache. Data are usually scattered more in the memory compared to the instructions, for this reason D-cache usually exhibit lower hit rates. Increasing its associativity will help to overcome the disparity in the hit rates. (12 marks) (d) Speculative execution (execution of instruction well ahead of the "present" instructions) requires presence of additional CPU registers that will hold the results that later may be or not be discarded. Bigger register file provides more room for instructions to speculate thus potentially improving the performance. Bigger physical register file comes at the cost of higher area required and higher power consumption. (6 marks) (e) TLB stands for Translation Lookaside Buffer - the cache memory used for keeping track of the virtual memory pages; whether they are present in the RAM or not. D and I stand for data and Instruction TLBs respectively. S most likely stands for the Shared TLB (between ITLB and DTLB). Virtual memory allows any application to use the complete address space for a given CPU for a limited amount of RAM actually installed, and even run several applications using the complete address space simultaneously