Q4. (10 pts) Sketch a schematic of the circuit described by the following HDL code using MUX2's. Write a testbench to verify the module below. module 94 (input [3:0] a, output reg (1:0) y); always @(*) if (a[0]) y = 2'511; else if(a[1]) y - 2'610; else if (a[2]) y = 2'601; else if (a (3]) y - 2'600; else y = a[1:0]; endmodule