Question 1)

a. Assume you have N items to process. If you can pipeline the processing into P steps (perfectly balancing the pipeline), what speedup is achieved? Explain all the steps used to arrive at your answer.

b. Consider the following RISCV code

add x5,x2,x1

lw x3,4(x5)

lw x2,0(x2)

or x3,x5,x3

sw x3,0(x5)

Rewrite this instruction sequence, inserting nop instructions, so it is free from hazards. You should assume standard 5-stage pipeline (instruction fetch, instruction decode / register fetch, execute, memory, write-back) with no forwarding or hazard detection. If registers are read in the same cycle in which they are written, the new value is returned. Draw a pipeline diagram to illustrate the correctness of your answer.

c. Using a figure, explain how the hazard between the or and sw instructions could be resolved by forwarding.

d. Explain in detail, the problem solved by the speculate and kill scheme in a pipelined processor.

e. Explain the concept of a write-after-read hazard. How can they be resolved without affecting performance in an out-of-order processor?

Question 2)

A computer system has a 128 byte cache. It uses four-way set-associative mapping with 8 bytes in each block. The physical address size is 32 bits, and the smallest addressable unit is 1 byte.

a. Draw a diagram showing the organization of the cache and indicating how physical addresses are related to cache tag, index and block.

b. To what sets of the cache can the address 0x000010AF be assigned?

c. If the addresses 0x000010AF and 0xFFFF7Axy can be simultaneously assigned to the same cache set, what values can the address digits x and y have?

d. Suppose in a virtual memory system that virtual addresses are 32 bits, the page size is 8 KB and the page entry size is 4 bytes. What is the total page table size for a single application that utilises half of the memory available?

e. What is a multilevel page table? Give one advantage and one disadvantage over a single level page table.

Question 3)

a. Consider a program that accesses a 10,000-word array of 32-bit integers in reverse order i.e. using indices 9999, 9998, , 1, 0. Assuming a 64 KB direct-mapped cache with 4- word blocks. Supported by a clear explanation, give an estimate of the miss rate due to compulsory misses, capacity misses and conflict misses.

b. Explain why, in general, cache block sizes which are too small or too large will lead to higher miss rates.

c. Explain the difference between a write-through and a write-back scheme. Which would be most appropriate for the virtual memory to disk interface?

d. Explain the differences between a cache miss and a page fault, particularly the response time required and how they are handled in a modern computer.

e. Explain using an example the issue of cache coherence. Is it an issue for single core processors?