QUESTION $1$

a$.$ Design implementation in the FPGA design flow for digital systems is a process by which the circuit descriped at generic logic gates level is turned into a configuration logic blocs or logic elements that define the FPGA devices in use $($Xilinx$,$ Altera, $...).$ At this step, a static timing $3$ pts analysis is perfomed and a timing simulation can be done using the generated back annotation file. What is the purpose of such file?

b$.$ In designing digital circuits what is the difference between abstraction levels and domain of

abstraction$?$

c$.$ In the IC$/$FPGA Design Flow what is the difference between Design entry and Design Synthesis. Explain the purpose of functional simulation in Figure $1?$

Figure $1$ : Part of IC$/$FPGA Design Flow

d$.$ What are the major differences between Actel, Xilinx and Altera FPGAs?