Question 2 (20 Points]- Verilog Operations Give the result of each Verilog expression (in binary) for the following inputs: A=4 'b0 100, B-3;bol 1, C-2'b00, D-4'b1 101, 2-4,b1xxx. Operator Nane bit-select or part-select b) IB C ) logical and bit-wise NOT c) A && B uaary (sign) plus, mis+17,-7 concatenation: (3'BI01.3 B110) -6 B101110 replication: {3(3'B110))9B1 10110110 multiply, divide, modubas;Land not he sparted Cor binary add, subtract bift left, shift right, Xc2 is maltiply by 4 comparisons. Reg and wire variables are taken as positive manbers logical equality, logikal loeguality case equality, case inequuanlity, pot sathesizablk bit-wise AND, AND together all the bits in a word bit-wise XOR, bit-wise XNOR bit-wise OR: AND tegether all the bits ia a word logical AND. Treat all variables as False (zero) or True (nouzero) logical OR Cio) is (TIE) -1. (1-3) is (TIT)-1 f) D