Question $2$

Grade

a$)$ Assume that the instruction set architecture $($ISA$)$ of the processor designed in the previous question $($Q$1)$ consists of $12$ assembly instructions. Specify the instruction size,

number of fields, and the size and name of each field for ADD R$2,$ R$3,$ RO$.$

b$)$ What is the machine code for ADD R$2,$ R$3,$ R$0?$ You can suggest an appropriate interpretation for the addition process but in a logical way.

Question $3$

i$)$ List the micro$-$instructions $($register transfer language instructions$)$ in the form of detailed flowcharts to execute the following instructions based on the design you have created in question $1$:

a$)$ MOV R$8,$ #$7$

b$)$ LOAD R$3,$ M$[$C$]$

ii$)$ Assume the clock rate of the CPU is $2GHz,$ where every step requires a number of clock cycles $($cc$)$ as shown in the table below. Calculate the execution time $($in ns$)$ for all instructions mentioned above.

Grade

$+10+10$

$+10)$

$1$

Concordia

$\backslash$table$[[$Internal Register Transfers,$1cc$