Case Study: Simplified Educational ISA Design

A team of computer science educators is designing a simplified Instruction Set Architecture $($ISA$)$ for use in introductory computer architecture courses. The goal is to help students understand the basics of ISA design, including the trade$-$offs between instruction complexity, memory addressing, and the limitations imposed by a fixed instruction width. The ISA, named EduISA, is characterized by the following design choices:

Fixed Instruction Width: All instructions are $8$ bits long, aiming to simplify the decoding process and instruction execution.

Register File: EduISA uses a minimalistic approach with $4$ general$-$purpose registers $($R$0$ to R$3),$ encoded with $2$ bits.

Instruction Set: EduISA includes a small set of instructions:

LOADI: Load an immediate value into a register. $($Opcode: $00)$

ADD: Add two register values and store the result in a third register. $($Opcode: $01)$

SUB: Subtract one register value from another and store the result in a third register. $($Opcode: $10)$

STORE: Store a register value into a memory location using direct addressing. $($Opcode: $11$; the instruction uses the next $8$ bits to specify the memory address, making it a $16-$bit instruction for this case only.$)$

Memory Addressing: EduISA supports direct addressing for the STORE instruction, allowing students to learn about memory operations. Due to the educational focus, a simplified memory model is used with addresses directly encoded in instructions when needed.

EduISA is intended to provide a hands$-$on learning experience, allowing students to write and execute simple programs that perform arithmetic operations and interact with memory.

Question $1(0\mathrm{.}5$ points$)$

Why does the STORE instruction in EduISA use a $16-$bit format?

Question $1$ options:

It is a design error and not intentional.

To provide extra space for encoding more complex operations.

To enable direct addressing of memory locations.

To allow for a larger range of immediate values.

Question $2(0\mathrm{.}5$ points$)$

What is the primary goal of the EduISA design?

Question $2$ options:

To facilitate learning about ISA design and operation.

To enable direct memory access for all instructions.

To support a wide range of complex instructions.

To maximize the performance of arithmetic operations.

Question $3(0\mathrm{.}5$ points$)$

EduISA's decision to limit registers to a $2-$bit encoding scheme impacts the processor's:

Question $3$ options:

Flexibility in register allocation and usage for optimizing program execution.

Ability to perform complex arithmetic operations directly in hardware.

Capacity for parallel processing and multi$-$threading.

Overall power consumption and chip complexity.

Question $4(0\mathrm{.}5$ points$)$

What design trade$-$off does the fixed $8-$bit instruction width in EduISA exemplify?

Question $4$ options:

A balance between decoding speed and the versatility of arithmetic operations.

A compromise between the number of available registers and the instruction set complexity.

A trade$-$off between instruction simplicity and the ability to directly address a wide memory range.

A trade$-$off between the instruction execution speed and memory access latency.

Question $5(3$ points$)$

Set$-$Associative Mapping Exercises

Scenario: $4-$way set$-$associative cache, $16-$bit address, $16$ sets, $2-$word block size.

Question: How many bits are used for the tag, set, and word IDs?

Question $5$ options:

Word ID:

Set ID:

Tag ID:

$($Optional$)$ reasoning:

Question $6(0\mathrm{.}5$ points$)$

You are writing a loop that should execute a fixed number of times, determined by the value $15.$ To set up the loop counter with this value, which addressing mode would you likely use?

Question $6$ options:

Indirect Addressing Mode

Immediate Addressing Mode

Direct Addressing Mode

Question $7(4$ points$)$

Advanced Assembly Programming with Bitwise and Conditional Instructions

Objective: Dive deeper into assembly language programming by tackling scenarios that necessitate the use of bitwise operations and conditional branching, enriching understanding of practical instruction set applications.

Extended Instruction Set:

AND Rx$,$ Ry$,$ Rz: Executes a bitwise AND between the values in Ry and Rz$,$ storing the outcome in Rx$.$

OR Rx$,$ Ry$,$ Rz: Executes a bitwise OR between the values in Ry and Rz$,$ storing the outcome in Rx$.$

BNE Label: Branches to a specific label if the preceding comparison did not result in equality.

CMP Rx$,$ Ry: Compares the values in Rx and Ry$,$ preparing the stage for conditional branching based on the comparison's outcome.

Memory Table for Context:

Address Value

$5008$

$5014$

$5022$

$60015$

$60110$

Tasks:

a$.$ Develop pseudo$-$instructions to perform a bitwise AND operation on the values at memory locations $500$ and $501,$ and a bitwise OR operation on the values at $500$ and $502.$ Then, store the AND result in $503$ and the OR result in $504.$

b$.$ Construct pseudo$-$instructions to compare the values at memory locations $600$ and $601.$ If $600$ is greater, store $1$ in $602$; otherwise, store $0$ in $602.$

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Question $7$ options:

a: To perform the required bitwise operations and store the results, the sequence of pseudo$-$instructions is:

b: For the conditional comparison and storage based on the values at $600$ and $601,$ the necessary pseudo$-$instructions are:

Question $8(0\mathrm{.}5$ points$)$

In the context of condition codes, what is a primary use of the Carry $($C$)$ flag?

Question $8$ options:

To indicate that the processor is carrying out a new instruction

To show that the operation did not result in any data being carried

To trigger an interrupt when an operation completes

To signal that an arithmetic operation resulted in a carry out or borrow into the most significant bit

Question $9(0\mathrm{.}5$ points$)$

Which data transfer method allows the CPU to continue with other tasks after initiating a transfer, only being interrupted upon completion?

Question $9$ options:

Interrupt$-$driven I$/$O

Programmed I$/$O

Synchronous Data Transfer

Direct Memory Access $($DMA$)$

Question $10(0\mathrm{.}5$ points$)$

Which of the following best describes the purpose of the Overflow $($V$)$ flag in a processor's status register?

Question $10$ options:

To signal that an arithmetic operation has produced a result too large to be represented in the allotted number of bits

To indicate whether the processor is currently handling an overflow of instructions

To flag when the processor has overflowed its instruction set

To determine if the processor's memory is overflowing