Question 5: Consider a pipeline with the following stages and latencies (in ps): Consider the following code is run on the processor with the pipeline described above: addi $r4, Szero, 100 loop: lw Sr0,0(Sr1) addi $r1,Sr0,1 sw $r1,0($r3) addi Sr4,Sr4,1 bne $r4, \$zero, loop a. What is the latency of a single instruction in a fully pipelined implementation? In a single cycle implementation? b. Assuming no forwarding, add NOP instructions to the code to remove any data hazards. The register file is read in the EX1 stage, and instructions must exit from WB for other instructions to use its value. c. What is the speedup of the fully pipelined implementation over the single cycle implementation? Assume steady-state execution. d. What are the possible forwarding paths? Assume data is ready to be forwarded at the end of its final stage (EX2, MEM3). e. Assuming all possible forwarding paths are implemented, what is the new speedup of the ful ipelined implementation over the single cycle implementation? Assume again steally tate execution