Register (register-memory) Load R1,A Add R3,R1,B Store R3 , C Stack Push A Push B Add Pop C Accumulator Load A Add B Store Register (load-store) Load R1,A Load R2,B Add R3, R1, R2 Store R3 , C Figure A.2 The code sequence for C A + B for four classes of instruction sets. Note that the Add instruction has implicit operands for stack and accumulator architectures and explicit operands for register architectures. It is assumed that A, B, and C all belong in memory and that the values of A and B cannot be destroyed. Figure A.1 shows the Add operation for each class of architecture. 1. For the following assume that values A, B, C and D reside in memory. Also assume that instruction operation codes are represented in 8 bits, memory addresses are 64 bits, and register addresses are 6 bits. For each instruction set architecture shown in Figure A.2 (of the textbook), how many addresses, or names, appear in each instruction for the code to compute following instructions and what is the total code size? (Please fill in the blanks in the following tables with your answers, add additional rows to tables if necessary) C- B+D-A Accumulator | # of addresses in the instruction Code size Total code size: ? bits