Required Urgently!!

1. Design a Verilog module with a 4-bit input array in [3:0] and a 4-bit output array out [3:0] to implement the following combinational circuit. If the input - as a non-negative number in unsigned binary representation - is not greater than 3, then the output is one greater than the input. Otherwise the output is one smaller than the input. Use a casex statement with only two cases. Call your module "plusminus