SEMtel" company recently launched a new processor with L$1$ cache and main memory for embedded applications. Specification of cache and main memory is tabulated in the following table

Cache memory capacity

$1$ K lines

Cache line size

$256$ Bytes

Hit Ratio

$85\%$

Associativity

$2-$way

Main memory capacity Main memory addressability

$8$ K Blocks

Memory Ordering

Byte addressable

Big$-$endian

Answer the following questions:

What is the capacity cache and main memory in terms bytes? $[0\mathrm{.}5+0\mathrm{.}5$ Marks$]$

$($ii$)$ How many lines are there in each set? $[0\mathrm{.}5$ Mark$]$

$($iii$)$ Specify the address format in terms Tag. Set and Word. $[0\mathrm{.}5+0\mathrm{.}5+0\mathrm{.}5$ Marks$]$

$($iv$)$ Let the cache access time is $0\mathrm{.}025$ ms and main memory access time is $0\mathrm{.}125$ ms$.$ What is the average memory access time? $[1$ Mark$]$

$($v$)$ How data $1356$H is stored in the main memory? Assame starting address of the memory is $1000$H$.[1$ Mark$]$