Show the state graph of the control unit FSM. Show where in the datapth you are checking the condition. B) Fill-in the control word table the control signals to be asserted to the Datapath inputs 0 through 15 in every cycle. The Table is provided in the solution section for your convenience.

There are two algorithms, and you can use either of these two. The second one needs only a one wire to check the condition, whereas the second one needs 8-input NOR gate). At this point, say, we dont care about this difference Just copy /paste the algorithm you used into your solution, so I know which one you followed. Algorithm 1: count = 0 input n while n > 0: { count = count + 1 n = n & (n-1) } output count Algorithm 2: (checking the least significant bit for 1 and adding it to count, easy condition logic, as it is a wire) count =0 Input n while n { if LSB(n) =1 { count=count+1 n=n>>1 } output count Grading contract: State graph: 1 point; Control Word Table 2 points

A) Show the state graph of the control unit FSM. Show where in the datapth you are checking the condition. B) Fill-in the control word table the control signals to be asserted to the Datapath inputs 0 through 15 in every cycle. The Table is provided in the solution section for your convenience. There are two algorithms, and you can use either of these two. The second one needs only a one wire to check the condition, whereas the second one needs 8-input NOR gate). At this point, say, we don't care about this difference Just copy/paste the algorithm you used into your solution, so I know which one you followed. Algorithm 1: count =0 input n while n>0 : {count=count+1n=n&(n1) outputcount 3 Algorithm 2: (checking the least significant bit for 1 and adding it to count, easy condition logic, as it is a wire) count =0 Input n while n=0 \{ if LSB(n)=1 \{ count = count +1 n=n>>1 \} output count Grading contract: State graph: 1 point; Control Word Table 2 points A) Show the state graph of the control unit FSM. Show where in the datapth you are checking the condition. B) Fill-in the control word table the control signals to be asserted to the Datapath inputs 0 through 15 in every cycle. The Table is provided in the solution section for your convenience. There are two algorithms, and you can use either of these two. The second one needs only a one wire to check the condition, whereas the second one needs 8-input NOR gate). At this point, say, we don't care about this difference Just copy/paste the algorithm you used into your solution, so I know which one you followed. Algorithm 1: count =0 input n while n>0 : {count=count+1n=n&(n1) outputcount 3 Algorithm 2: (checking the least significant bit for 1 and adding it to count, easy condition logic, as it is a wire) count =0 Input n while n=0 \{ if LSB(n)=1 \{ count = count +1 n=n>>1 \} output count Grading contract: State graph: 1 point; Control Word Table 2 points