shows the datapath that you had to work with in the last lab. Let us discuss the new operations

and what changes need to happen to support them:

$$ Add$/$subtract immediate $($addi$/$subi$)$ The datapath changes are the same for these two new

operations, so we will discuss them together. The $$normal$$ add$/$sub operations $($the ones you

implemented in the last lab$)$ read a value from the RF and capture it into staging latch A$,$ and

then read a second operand from the RF that is used by the secondary input of the adder. In

the case of this new operation, the first operand is still read from the RF and captured in staging

latch A$.$ But the data for the secondary input to the adder needs to be the data coming from

the immediate $($Imm$)$ field of the instruction $($i$.$e$.,$ addi causes X $=$ X $+$ Imm while subi causes

X $=$ X $$ Imm.$)$ So we will need a pathway for that data to reach the secondary input to the

adder, without breaking the support for the register$-$based add or the support for the load

operation.

$$ Display $$You need to implement a holding latch $($not unlike latch A and latch G in the diagram

above$)$ that gets loaded by the display operation with the contents of whatever register is

specified by AddrX as part of the operation. Again, the idea is that the value in this memory

would be displayed on a screen $($not really, but conceptually$).$ If you want to display a different

value, you will need to execute another display operation. Relative to the diagram above, you

will need to define where this new latch will be added and how data from the RF can be loaded

into it$.$

Changes to the datapath

Given the new operations that we are looking to implement, it needs to change. To support the newly

added instructions, we need to add two more Verilog modules as depicted in Figure $2.$ That is$,$

$$ MUX $$ Previously, the second $4-$bit operand of the adder always came from the RF$.$ On the

other hand, we now must selectively feed the data from the Imm field of the instruction $($for

addi and subi$)$ or from the RF$$s DataOut $($for the other instructions$).$ A $4-$bit $2-$to$-1$ MUX

$($mux$\_2\_$to$\_1.$v$)$ in added in the datapath for this purpose. While the source code of this MUX

is given in a completed form, take the time to look at the source code; it is worth having a look

as it is written in a generic way to support any bit lengths. I.e$.,$ the same implementation can

be reused without any modification for different big lengths such as $16-$bit or $32-$bit$\mathrm{.}1$ Through

this MUX, DataOut from the RF is connected to the second operand of Adder if Iout is $0.$ On

the other hand, when Iout is $1,$ Imm is the second operand that Adder gets.

$$ Latch DP $$ For the display latch, you can reuse the latch code $($A$.$v$)$ that was used for latch A

and latch G in Lab $2.$ The enable input $($DPin$)$ of this latch should be properly controlled by

the control logic.

$$ Control logic $$ The control state machine needs to be modified properly with two additional

control output signals $($Iout and DPin$).$

Extending Opcode

In Lab $2,$ we used a $2-$bit opcode to specify which operation to perform. Now that we are adding three

new operations, we need to add another bit to our opcode. This will give us a $3-$bit value for the

purposes of specifying the operation to perform, which in turn means that you will need to extend the

specification of your encodings for all the possible operations, so that each is now a unique $3-$bit

value. And your state machine, which is dependent on properly decoding the specified operation, will

need to account for the new encoding specification. We assume the following extended encoding for

opcode $($operation in l$3\_$SM$.$v$)$:

$3$b$000$: load

$3$b$001$: move

$3$b$010$: subtract

$3$b$011$: add

$3$b$100$: display

$3$b$101$: $($reserved$,$ i$.$e$.,$ not used for now$)$

$3$b$110$: subi

$3$b$111$: addi

With this extended opcode, we have an $11-$bit instruction format for this datapath as illustrated below:

II$.$ PRE$-$LAB

$($i$)$ Based on the updated block diagram $($Figure $2)$ and instruction format $($Figure $3)$ which show

the datapath support for the new operations, properly modify the module interface of l$3\_$SM$.$v