Sketch a schematic of the Circuit described by the following VHDL code. library IEEE: use IEEE.STD_LOGIC_1164.all: entity exercisel is port(a, b, c: in STD_LOGIC; y, z: out $TD_LOGIC); end; architecture synth of exercisel is begin y leftarrow (a and b and c) or (a and b and (not c)); z