So below i have 3 vhdl module for a division circuit. I have the entity part for the module, now i need the behavirol part of the codes.

| P a g e 1. You first need to create an ALU module similar to the following: entity ALU is Port ( I_ALU_EN : in STD_LOGIC; I_ALU_A : in STD_LOGIC_VECTOR (5 downto 0); I_ALU_B : in STD_LOGIC_VECTOR (5 downto 0); O_ALU_Out : out STD_LOGIC_VECTOR (5 downto 0); O_ALU_Flag : out STD_LOGIC ); end ALU; I_ALU_EN: used to enable the ALU I_ALU_A: the first input of the ALU I_ALU_B: the second input of the ALU O_ALU_Out: the output of the ALU O_ALU_Flag: the bit that indicates which input is bigger, used to set the LSB of the Register 2. You then need to create the Register module entity DivRegister is Port ( I_REG_Init : in STD_LOGIC; I_REG_Update: in STD_LOGIC; I_REG_SLL : in STD_LOGIC; I_REG_LSB : in STD_LOGIC; I_REG_Div : in STD_LOGIC_VECTOR (5 downto 0); I_REG_ALU : in STD_LOGIC_VECTOR (5 downto 0); O_REG_HI : out STD_LOGIC_VECTOR (5 downto 0); O_REG_LO : out STD_LOGIC_VECTOR (5 downto 0) ); end DivRegister; I_REG_Init: control signal to let the register initialize its contents I_REG_Update: control signal to let the register update its contents I_REG_SLL: control signal to let the register perform a shift I_REG_LSB: used to set the LSB of the register I_REG_Div: pass Dividend to the register I_REG_ALU: pass ALU output to the register O_REG_HI: the output of HI O_REG_LO: the output of LO 3. Next you need to create the control logic entity Control is Port ( I_CTL_CLK : in STD_LOGIC; I_CTL_EN : in STD_LOGIC; O_CTL_ALU : out STD_LOGIC; O_CTL_RMD : out STD_lOGIC; O_CTL_SLL : out STD_LOGIC;

); end Control; I_CTL_CLK: the clock that drives the control unit I_CTL_EN: the signal that enables the control unit O_CTL_ALU: the control signal that enables the ALU O_CTL_RMD: the control signal that triggers the update of the register O_CTL_SLL: the control signal that triggers the shift of the register O_CTL_INI: the control signal that triggers the initialization of the register In the control unit, you will also need to create a state machine with multiple states. In each state, you may want to signal the modules to perform the proper tasks (e.g. Register shift, Register update, ALU operation, etc.). Note that you may want to update the state machine at the rising edge of a CLK, e.g. if rising_edge(I_CTL_CLK) then -- control logic end if;