solve it urgently

Q2. Consider a direct mapped cache with 1 MB of data and 8-word block size with 33 bits address. (a) Draw the flow diagram of the DMC and calculate the Cache size (5 marks) (5 marks) (b) Assume for a given CPU/DMC and MIPS program: instruction cache miss rate 2% data cache miss rate 4% miss penalty always 40 cycles CPI of 2 without memory stalls (perfect cache) frequency of load/stores 36% of instructions How much faster is a CPU with a perfect cache that never misses