Soru 4 20 Puan A designer wants to design a synchronous logical circuit that has 3-bit input and a control input. Input bit contents transferred to the circuit only if the control signal is enabled. Once the input is accepted, the circuit checks If it is an odd number or not. Odd number yields the circuit starts counting forward by 2, and even number yields counting reverse by 3. Write down the Verilog HDL code for this circuit