SR LATCH & D LATCH 4.1 OBJECTIVE In this experiment we will construct a few simple latch circuits, and realize the truth tables. 4.2 EQUIPMENT LIST Digital Training set Y-0039, Logic Gates: 7404 Inverter, 7400 NAND gate, 7402 NOR gate, 7408 AND gate 4.3 PRELIMINARY WORK 1. What is D Latch? Explain. 4.4 PROCEDURE 1. Use two NOR gates to construct basic SR latch circuit shown in Figure 1. Connect R and Sinputs to switches A and B respectively. DO NOT FORGET to connect Vcc and Ground pins of ICs you used. Connect and Q and Q' to the Logic Indicator. Realize the truth table according to the inputs in Table 1. What happens SR=11 goes to SR=00? Table 4.1 R S ROQ 00 0 1 1 0 11 0 0 - Figure 4.1 2. Use two AND gates, two NOR gates and one INVERTER to construct the D latch circuit shown in Figure 2. Connect D and E (enable) to switches A and B respectively. DO NOT FORGET to connect VCC and Ground pins of ICs you used. Connect Q and Q' to the Logic Indicator. Realize the truth table according to the inputs in Table 2. Table 4.2 Q Comment ED Q 0 x 1 5 0 D 11 Figure 4.2 D Latch EE242 Digital Systems Laboratory Altnba University Departmant of Electrical and Electronics Engineering 1 4.5 QUESTIONS 1. What is level sensitive SR latch? 2. Draw Dlatch and give the outputs of the gates (every gate) for some inputs. 3. What is the problem when SR=11 then SR=00 in a basic SR latch? How can you solve this problem? 4. Give some information about D latch