Study questions

Which I/O scheme is least efficient (that is, wastes CPU cycles )? OB. VO devices that can be bus masters O C. Interrupt driven lio O D. Programmed I/O with busy waiting (looping for device ready) O E. DMA l/O UESTION 6 In the Pentium 4 processor, the ISA level instructions: 0 A are virtual O B. have only 2 addressing modes C. are variable length O D. are fixed length O E. are RISC-like (simple format) UESTION 7 Let's say that you have a 1.0 Gigabyte hard disk formatted with some filesystem (like FAT). You load about 1000 1.0 kilobyte files on the drive (1.0 Megabytes total). The computer then gives you an error message saying that the hard disk is full. What is the 'most likely* problem? O A. The hard disk has crashed O B. The VM system has failed C. The directory size was set too small O D.he MMU unit needs to be reset O E. The cluster size was set too large UESTION 8 The addressing mode in which the address of the operand is given in the instruction is O A direct addressing 0 B, based-indexed register addressing C. trap addressing 0 D. register addressing O E. indexed addressing Which I/O scheme is least efficient (that is, wastes CPU cycles )? OB. VO devices that can be bus masters O C. Interrupt driven lio O D. Programmed I/O with busy waiting (looping for device ready) O E. DMA l/O UESTION 6 In the Pentium 4 processor, the ISA level instructions: 0 A are virtual O B. have only 2 addressing modes C. are variable length O D. are fixed length O E. are RISC-like (simple format) UESTION 7 Let's say that you have a 1.0 Gigabyte hard disk formatted with some filesystem (like FAT). You load about 1000 1.0 kilobyte files on the drive (1.0 Megabytes total). The computer then gives you an error message saying that the hard disk is full. What is the 'most likely* problem? O A. The hard disk has crashed O B. The VM system has failed C. The directory size was set too small O D.he MMU unit needs to be reset O E. The cluster size was set too large UESTION 8 The addressing mode in which the address of the operand is given in the instruction is O A direct addressing 0 B, based-indexed register addressing C. trap addressing 0 D. register addressing O E. indexed addressing